Last year, we tried shooting a few fireworks at a probe card to show how tough it was. We thought that test went okay, but we thought it would be fun to use a little more fire power.
So we picked up a box of 45 various (Minnesota legal) fireworks, lined them off, and lit our kludged fuse. This is what happened.
Embedded below for viewers outside of the US.
Destroying Probe Cards
How tough are Celadon probe cards, really? We took the opportunity to soak up some of the hot Minnesota summer sun to see.
As you can see above, we shot fireworks at one of our cards – it survived handily, so we decided we need to do that again, with a lot more fireworks.
Another test that we did was taking an internal connector card and placing it on a barbecue. In a continuous shot (sped up a lot at points), here’s what happened.
So, as you can see from the video, the card survived temperatures that were as hot as 200°C (we didn’t crank the grill up more, because we were also cooking lunch!), and aside from a lot of debris from the grill, the ceramic was intact and the probes were in essentially the same position as they were before.
Are there any other tests you’d like us to do with probe cards? Leave a suggestion in the comments, and we’ll film our favorite ideas!
Celadon designs two-site parametric probe card
The real fun of engineering is when we’re given the opportunity to push the boundaries of what we’ve come to think of as normal. Recently, one of our customers, who was already using our VersaCore™ production parametric probe cards,…
Celadon NIST Research Grant
We’re pleased to announce that Celadon was a recipient of a NIST (National Institute of Standards and Technology) research grant to study means of accurately conducting high-temperature-and-volume WLR tests as wafers continue to get smaller and smaller. The past ten years have seen incredible growth and innovation in the semiconductor industry, and we’re excited that with this grant, we have an opportunity to make sure the innovation of semiconductor testing keeps pace with an improved method of performing wafer level reliability tests. If you have any questions or comments, please feel free to get in touch with Joe at email@example.com.