This past April, we attended the 2011 IRPS convention in Monterey, CA. After all the presentations wrapped up, and the last of the cookies at our booth were eaten, we had a chance to speak with some of the people involved, and what they saw as significant ideas presented during the convention (full program here).
IEEE General Chair Jim Stathis was happy, especially with the evening poster session hosted at the Monterey Aquarium. “It was encouraging that attendants spent the entire evening of the poster session asking questions from presenters. People could have gone around looking at all the different wings of the aquarium, but the poster floor was crowded right until the end of the night.”
Joe McPherson, who led a reliability tutorial, said the poster session was also a great opportunity to talk with people he hadn’t seen in a while. The evening, and the conference in general, was a “free exchange of ideas.”
As a general chair, Stathis wasn’t able to see many of the presentations, but he was impressed with what he was able to see. “Researchers from TSMC presented a paper, [Re-investigation of Gate Oxide Breakdown on Logic Circuit Reliability], that made some very good arguments that circuit performance isn’t affected by oxide breakdown.” Stathis said it was gratifying to see other researchers expanding on his 2001 paper, “Physical and Predictive Models of Ultrathin Oxide Reliability in CMOS Devices and Circuits.”
“Breakthroughs don’t come every year,” said McPherson. One idea that intrigued him, though, was the idea that in NBTI, traps may be pre-existing in gate oxide instead of being a result of the silicon-hydrogen bond breaking. “No-one’s sure if it’s true, but the old model is one we’ve been using the last decade or so, and we’ll see how it sorts out over the next few years.”
Breakthroughs may not come every year at IRPS. But at the Celadon booth, cookies do.